Method and device for processing semiconductor wafer

ABSTRACT

A method of processing a semiconductor wafer including the steps of executing a permutation processing by using a plurality of processing containers while sequentially transferring the wafers into the containers or performing a parallel processing and a transfer mechanism used commonly for the containers while sequentially transferring the wafers. The wafer processing is performed after the completion of conditioning of the vessel, and a conditioning start time for a next container is adjusted so that the completion of conditioning occurs when processing in the previous container is completed.

FIELD OF THE INVENTION

The present invention relates to a method and device for processing asemiconductor wafer by using a plurality of processing vessels forperforming processes such as a film formation on the semiconductorwafer.

BACKGROUND OF THE INVENTION

In general a processing of semiconductor wafers is carried out bytransferring semiconductor wafers into a plurality of processing vessels(chambers) prepared in a processing device by a transfer mechanism. Forsuch processing of semiconductor wafers there are a sequentialprocessing and a parallel processing. The sequential processing isperformed by using a plurality of processing vessels each for executingdifferent process, wherein a semiconductor wafer is sequentiallytransferred through the processing vessels. On the other hand, theparallel processing is performed by using a plurality of processingvessels for carrying out an identical process (e.g., a film formationprocess) and a transfer mechanism used therefor in common, whereinsemiconductor wafers are sequentially transferred to the respectiveprocessing vessels by the transfer mechanism and the identical processis performed on respective wafers therein. The different processes inthe sequential processing may include separate processes, e.g., a filmformation process and an etching process, or a film formation processfor forming films with different elements, e.g., Ti, TiN, W, WSi or thelike, even in a single film formation process.

In both processing methods, temperature, pressure and other parametersin each processing vessel are controlled to be in a conditionappropriate for adequately processing the semiconductor wafers, prior toloading the semiconductor wafers into the processing vessels.Hereinafter, controlling conditions of each processing vessel beforeperforming a process will be referred to as conditioning. Suchconditioning includes, e.g., a cleaning or a precoating performed aftercreating in a processing vessel the same atmosphere as in performing aprocess therein.

Conditioning times vary depending on the processing vessels. Forinstance, when process temperatures of the respective processing vesselsare different from each other, the amount of time needed to raise thetemperature to different process temperatures vary accordingly. Further,in case of performing different processes in the respective processingvessels, the cleaning times are different and, therefore, conditioningtimes are different. Moreover, since the cleaning times are determinedbased on the number of wafers to be loaded into the respectiveprocessing vessels in the aforementioned parallel processing, thecleaning times of the processing vessels are different from each other,making the conditioning times thereof different from each other.

In the conventional sequential processing as described above, theconditionings are started simultaneously in all processing vessels A toD, as shown in FIG. 8. Specifically, upon completion of conditioningS_(D) of processing vessel D, which has the longest conditioning time S,the wafer is transferred to a first processing vessel A and then aprocessing P_(A) is performed thereon. When a process P is completed ina preceding processing vessel, a transferring C of the wafer to asubsequent processing vessel is executed and a process P is performedtherein.

As described above, by synchronizing the conditionings to startsimultaneously in all processing vessels, there occur waiting timeW_(A), W_(B), W_(C) and W_(D) between the time of completing theconditionings of the processing vessels and the time of starting thetransferring of the wafers, which are different from each other.

For instance, though a process is first performed in the processingvessel A, the waiting time W_(A) occurs until the conditioning timeS_(D) of the processing vessel D, which takes the longest time, lapses.Further, despite the long conditioning time S_(D) of the processingvessel D and a processing P_(D) thereof is performed last, there occursa long wait time W_(D) of the processing vessel D until the processes ofthe other processing vessels A to C are completed, since theconditioning thereof is started early.

As explained above, if there occur the different waiting time W_(A),W_(B), W_(C) and W_(D) in the processing vessels A to D, respectively,after finishing the conditionings thereof, an inner state of eachprocessing vessel may undergo a subtle change before the wafer is loadedthereinto. In particular, the different waiting time period cause thetemperature of each processing vessel (a temperature of a susceptorinstalled in each processing vessel or a temperature of each processingvessel affected by radiation of the susceptor) to be delicately changed,so that the temperatures of the processing vessels deviate from presettemperatures. Similarly in the above-described parallel processing,since the conditionings are simultaneously initiated in all processingvessels X, Y and Z, e.g., shown in FIG. 9, the different waiting time(W_(X)=0), W_(Y) and W_(Z) are generated. Thus, there is a problem withthe processing results of the respective processing vessels, e.g., thethickness of films formed on a wafer delicately vary.

While sequentially processing a plurality of wafers, such a problem ismost noticeable in a first processed wafer. The environment of eachprocessing vessel is considered to be relatively more stable by the timeof executing processing on the second wafer, compared to that during theprocessing of the first wafer. And during the processing of the firstwafer, the environment is considered unstable.

Recently, a manufacturing of a semiconductor having a high accuracy isrequired with an advancement of a semiconductor product, whichaccompanies a demand for further improvement in accuracy in processing asemiconductor wafer, e.g., uniformity of a film formation or the like.

SUMMARY OF THE INVENTION

It is, therefore, an object of the present invention to provide a methodand device for processing a semiconductor wafer, which enables areliable process by preventing non-uniformity of inner states of aplurality of processing vessels caused by differences in waiting timebetween the processing vessels, i.e., differences in time betweencompletion of conditionings of the processing vessels and the transferof the wafers thereinto.

In accordance with one aspect of the invention, there is provided asemiconductor wafer processing for performing a sequential processing byusing a plurality of processing vessels performing processes differentfrom each other, the sequential processing being carried out bysequentially transferring a semiconductor wafer through the processingvessels, wherein a wafer processing in each processing vessel isperformed after completing a conditioning of each processing vessel andwherein a start time of a conditioning of a next processing vessel iscontrolled such that the conditioning of the next processing vessel iscompleted in harmony with a completion of a processing of a precedingprocessing vessel.

By the above method, time intervals of the processing vessels betweenthe completion times of the conditionings and start times of theprocesses can be made to be identical to each other and waiting timeoccurring after the completion of the conditionings can be considerablyreduced.

In such case, it is preferable that a processing vessel to be initiallyconditioned is determined stepwise by comparing a conditioning time S ofa specific processing vessel with a summation time T to determine abigger one among the times S and T, the summation time T being a sum ofa transferring time and a processing time of the wafer for each of oneor more preceding processing vessels in which a processing is carriedout prior to the specific processing vessel and a conditioning time of aprocessing vessel for performing a processing first through thepreceding processing vessels.

In accordance with another aspect of the invention, there is provided asemiconductor wafer processing method for performing a parallelprocessing by employing a plurality of processing vessels performing anidentical processing and a transfer mechanism commonly used for theprocessing vessels, the parallel processing being carried out bysequentially transferring semiconductor wafers to the respectiveprocessing vessels by the transfer mechanism and performing theidentical processing on a semiconductor wafer in each of the processingvessels, wherein a wafer processing in each processing vessel isperformed after completing a conditioning of each processing vessel andwherein a start time of a conditioning of a processing vessel iscontrolled such that the conditioning of the processing vessel iscompleted in harmony with a completion of a transferring of a wafer to apreceding processing vessel to which a wafer transferring is carried outprior to the former processing vessel.

By the above method, time intervals of the processing vessels betweenthe completion times of the conditionings and start times of theprocesses can be made to be identical to each other and waiting timeoccurring after the completion of the conditionings can be considerablyreduced.

In such case, it is preferable that conditionings are sequentiallyinitiated in the processing vessels in an ascending order ofconditioning times.

Doing so enables shortening of the whole time period for the parallelprocessing by using the plurality of processing vessels and anenhancement of processing efficiency.

In accordance with yet another aspect of the invention, there isprovided a semiconductor wafer processing method by using a plurality ofprocessing vessels, wherein a wafer is transferred into each processingvessel and processed therein after completing a conditioning of eachprocessing vessel and wherein start times of conditionings of theprocessing vessels are controlled such that time intervals betweencompletion times of the conditionings and processing start times in therespective processing vessel are identical to each other.

By performing the processing by the above method, the variation in timeintervals between the completion times of the conditionings and thestart times of the processes can be corrected.

Further, in accordance with the processing method of the presentinvention, the promoted processing efficiency enables reduction ofconsumption of a processing gas or energy such as a power.

In accordance with still another aspect of the invention, there isprovided a semiconductor wafer processing device including a pluralityof processing vessels configured for performing processings differentfrom each other on a semiconductor wafer, a conditioning of eachprocessing vessel being performed before starting a processing thereof,and a transfer mechanism for transferring the wafer through theprocessing vessels, wherein a sequential processing is performed whilesequentially transferring the wafer through the processing vessels byusing the transfer mechanism, a calculating unit for calculating, foreach processing vessel, a start time of a conditioning of a nextprocessing vessel such that the conditioning of the next processingvessel is completed in harmony with a completion of a processing of apreceding processing vessel, and a conditioning control unit forstarting conditionings of the respective processing vessels according tostart times calculated by the calculating unit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic horizontal sectional view of an exemplarydevice for executing a method for processing a wafer in accordance witha preferred embodiment of the present invention;

FIG. 2 gives a schematic side elevational view of the wafer processingdevice shown in FIG. 1;

FIG. 3 offers a flow chart for illustrating a sequential processing forcontrolling start of conditionings of respective processing vessels byusing the wafer processing device shown in FIG. 1;

FIG. 4 presents a timing diagram of a case using the process illustratedin FIG. 3;

FIG. 5 provides a flow chart for describing a comparison process ofconditioning times of the respective processing vessels in executing aparallel processing by using the wafer processing device illustrated inFIG. 1;

FIG. 6 offers a flow chart for describing a comparison process of theconditioning times of the respective processing vessels in case that aprocessing result of FIG. 5 is S13<S12<S11;

FIG. 7 provides a timing diagram of the processes presented in FIGS. 5and 6;

FIG. 7A shows a part of a process for controlling the starts of theconditionings when performing subsequent processes;

FIG. 8 gives a timing diagram of a sequential processing in accordancewith a conventional wafer processing method; and

FIG. 9 offers a timing diagram of a parallel processing in accordancewith a conventional wafer processing method.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The preferred embodiments of the present invention will be described indetail with reference to the accompanying drawings.

Processing Device

FIGS. 1 and 2 are a horizontal sectional view and a side elevationalview, respectively, schematically showing a wafer processing device 1of, so called, multi-chamber type, including a plurality of processingvessels (chambers). Referring to FIGS. 1 and 2, the whole structure ofthe processing device 1 will now be described.

The processing device 1 is provided with a vacuum transfer chamber 4,two load lock chambers 6, 8 and four vacuum processing vessels(processing modules) A to D. FIG. 2 shows a state in which theprocessing vessels A to D have been detached from the processing device1. The load lock chambers 6, 8 and the processing vessels A to Ddisposed around the transfer chamber 4 are connected thereto via gatevalves G1 to G6, respectively. Installed in the transfer chamber 4 is atransfer arm 2 serving as a transfer mechanism for transferring asemiconductor wafer H and commonly used for the load lock chambers 6, 8and the processing vessels A to D.

The respective processing vessels A to D are configured, e.g., toperform therein different processes from each other. The differentprocesses may include different types of processes such as a filmformation process and an etching process, or a film formation processfor forming films with different materials, e.g., Ti, TiN, W, WSi or thelike, in a single film formation process. Under such configuration, thesequential processing can be performed by transferring the wafer Hthrough the processing vessels A to D in sequence. On the other hand,the processing vessels A to D can be configured in such a manner as toperform therein an identical process (e.g., a Ti film formationprocess). Also under such configuration, the parallel processing forperforming a same process on respective wafers H can be carried out ineach of the processing vessels A to D by transferring the respectivewafers H thereto in order.

The load lock chambers 6, 8 are used for transferring the respectivewafers H between a depressurized ambient of the transfer chamber 4 andan atmospheric ambient outside the transfer chamber 4, while maintaininga depressurized state inside the transfer chamber 4. The load lockchambers 6, 8 are designed to appropriately set ambient pressure thereofby employing a pressure control unit 18 (see FIG. 2) installed beneaththe load lock chambers 6, 8, which includes a vacuum pump and a gassupplying system. The load lock chambers 6, 8 have openings leading tothe outside, which are hermetically sealed to be opened and closed bygate valves G7 and G8, respectively. The opening and closing operationsof the gate valves G7, G8 are carried out by raising and lowering valvebodies which make up the respective gate valves by using a driving unit(not shown).

There is provided in the processing device 1 a controller (a calculatingunit, a condition control unit) (not shown) for controlling theoperation of each of the units and performing a calculation. Thecontroller includes a CPU (central processing unit), a ROM for storing,e.g., program data, enabling the CPU to control the operation of eachunit and a RAM for providing a memory area for the CPU's dataprocessing.

Sequential Processing

Hereinafter, there will be explained the sequential processing of awafer by using the processing device 1 having the processing vessels Ato D which perform therein the different processes from each other. Inexecuting the sequential processing, the wafer is transferred to each ofthe processing vessels A to D in sequence by a transfer arm 2 under thecontrol of the controller. Prior to transferring the wafer into therespective processing vessels A to D, conditioning such as cleaning,precoating and the like is performed so that conditions suitable forperforming desired processes therein is established by controlling thetemperature, pressure and other parameters thereof.

Herein, a conditioning performed prior to processing a first wafer inexecuting the sequential processing of a plurality of wafers will bedescribed. There are shown in FIG. 3 a control mechanism of thecontroller up until the start of an execution of the conditioning of theprocessing vessels A to D thereby and in FIG. 4 an exemplary timingdiagram of the sequential processing based on the control mechanismillustrated in FIG. 3. Referring to FIG. 4, S1 to S4 represent theamount of time required for performing the conditionings of therespective processing vessels A to D; and P1 to P4 represent the amountof time required for performing respective processes in the processingvessels A to D. Further, C1 to C4 are the amount of time required fortransferring the wafer to the processing vessels A to D (time intervalbetween completion of the conditioning and start of the process).Further, D1 to D4 are waiting times (delay times to be described later)designed to control starting points of the conditionings of therespective processing vessels A to D.

Referring to FIG. 3, the controller selects through the steps ST1 toST16 a vessel in which a conditioning is to be initially performed.First, in the step ST1, the controller detects inner state of theprocessing vessels A to D, respectively, and then calculates theconditioning time S1 to S4 required to achieve an appropriate innerstate for performing desired processes based on the detected innerstate. For example, by detecting the temperature of a heater installedin each of the processing vessels A to D, a difference between thecurrent temperature and the temperature appropriate to perform a processis obtained. Based on the thus obtained difference and a rate of rise ofthe temperature previously stored in, e.g., a memory, calculations areperformed to obtain the amount of time required for controlling theinner states of the processing vessels appropriate for processes. Thecalculated time periods are represented by conditioning time S1 to S4.

Next, in the step ST2, a sum (S1+C1+P1) of the conditioning time S1, thetransferring time C1 and the processing time P1 of the processing vesselA where a process is first performed is compared with the conditioningtime S2 of the processing vessel B where a process is subsequentlyperformed. If S1+C1+P1 is less than S2 (S1 +C1+P1<S2), the sum of thetime periods in the processing vessel B (S2+C2+P2) is compared with theconditioning time S3 of the processing vessel C where a process isperformed following the process of the processing vessel B, in the stepST3.

In the step ST3, if S2+C2+P2 is less than S3 (S2+C2+P2<S3), the sum ofthe time periods of the processing vessel C (S3+C3+P3) is compared withthe conditioning time S4 of the processing vessel D where the process islast performed. If S3+C3+P3 is less than S4 (S3+C3+P3<S4), theprocessing vessel D is determined in the step ST5 as a processing vesselto be first conditioned and the conditioning thereof is started in thestep ST17. In this case, the reason for initiating the conditioning ofthe processing vessel D first is that the processes (including theconditioning, transferring and processing) in the processing vessels Ato C can be finished while performing the conditioning thereof.

If S3+C3+P3 is greater than S4 (S3+C3+P3>S4) in the step ST4, theprocessing vessel C is determined in the step ST6 as a first processingvessel to be conditioned, and a conditioning thereof is started in thestep ST17. In this case, the reason of initiating the conditioning ofthe processing vessel C is that the processes in the processing vesselsA and B can be completed while performing the conditioning thereof, andthe conditioning of the processing vessel D can be finished whileperforming the conditioning and the process thereof.

On the other hand, if S2+C2+P2 is greater than S3 (S2+C2+P2>S3) in thestep ST3, the sum of the conditioning time S2, the transferring time C2and the processing time P2 of the processing vessel B, and thetransferring time C3 and the processing time P3 of the processing vesselC (S2+C2+P2+C3+P3) is compared with the conditioning time S4 of theprocessing vessel D in the step ST7. If S2+C2+P2+C3+P3 is less than S4(S2 +C2+P2+C3+P3<S4), the processing vessel D is determined in the stepST8 as the processing vessel in which a conditioning is to be firstexecuted and the conditioning thereof is started in the step ST17.However, if S2+C2+P2+C3+P3 is greater than S4 (S2+C2+P2+C3+P3>S4) in thestep ST7, the processing vessel B is determined in the step ST9 as aprocessing vessel to be conditioned first and the conditioning thereofis started in the processing vessel B in the step ST17.

Going back to the step ST2, if S1+C1+P1 is greater than S2(S1+C1+P1>S2), the sum of the conditioning time S1, the transferringtime C1 and the processing time P1 of the processing vessel A, and thetransferring time C2 and the processing time P2 of the processing vesselB is compared with the conditioning time S3 of the processing vessel Cin the step ST10. If S1+C1+P1+C2+P2 is less than S3 (S1+C1+P1+C2+P2<S3),the sum of the time of the processing vessel C (S3+C3+P3) is comparedwith the conditioning time S4 of the processing vessel D in the stepST11.

If S3+C3+P3 is less than S4 (S3+C3+P3<S4) in the step ST11, theprocessing vessel D is determined in step ST12 as a processing vessel tobe first conditioned, and the conditioning thereof is started in thestep ST17. However, if S3+C3+P3 is greater than S4 (S3+C3+P3>S4), theprocessing vessel C is determined in the step ST13 as a processingvessel where the conditioning is first performed and a conditioningthereof is started in the step ST17.

On the other hand, if S1+C1+P1+C2+P2 is greater than S3(S1+C1+P1+C2+P2>S3) in the step ST10, the sum of conditioning time S1 ofthe processing vessel A, transferring time and the processing time ofthe processing vessels A, B, C (S1+C1+P1+C2+P2+C3+P3) is compared withthe conditioning time S4 of the processing vessel D. IfS1+C1+P1+C2+P2+C3+P3 is less than S4 (S1+C1+P1+C2+P2+C3+P3<S4), theprocessing vessel D is determined in the step ST15 as a processingvessel to be first conditioned and the conditioning thereof is startedin the step ST17. However, if S1+C1+P1+C2+P2+C3+P3 is greater than S4(S1+C1+P1+C2+P2+C3+P3>S4) in the step 14, the processing vessel A ischosen in the step ST16 to be first conditioned and the conditioningthereof is initiated in the step ST17.

After initiating the conditioning in the first processing vessel in thestep ST17, delay times D, i.e., waiting times of the other processingvessels until the conditionings are started therein, are calculated.Once a processing vessel to be first conditioned is determined, thedelay times D can be calculated from the reference time which isdetermined based on the already calculated conditioning time S1 to S4,transferring time C1 to C4 and processing times P1 to P4 of therespective processing vessels A to D.

For example, referring to FIG. 4 showing the case in which aconditioning is first started in the processing vessel B, the completiontime of the process in the processing vessel C is set to be thereference time R. The delay time D1 of the processing vessel A isobtained by D1=R−(S1+C1+P1+C2+P2+C3+P3) and the delay time D3 of theprocessing vessel C is obtained by D3=R−(S3+C3 +P3). Further, the delaytime D4 is obtained by D4=R−S4.

Further, in the step ST19, the conditionings of the other processingvessels are initiated after the calculated delay time D has elapsed. Inthe case shown in FIG. 4, after a conditioning is first initiated in theprocessing vessel B, the conditionings of the processing vessels A, Cand D are initiated after the respective delay times D1, D3 and D4 haveelapsed.

As described above, a processing vessel in when a conditioning is to befirst started is determined based on the conditioning times S of theprocessing vessels (steps ST1 to ST16) and, simultaneously, the delaytimes D of the other processing vessels are calculated (step ST18). Thestarting times of the conditionings of the processing vessels areadjusted by using the delay times D so that a conditioning in asubsequent processing vessel and a process in a preceding processingvessel are ended at the same time (steps ST17 and ST19).

By controlling the starting times of the conditionings as the above, thevariation in time intervals between the ending point of the conditioningof a processing vessel and the starting point of the process of theprocessing vessel is not generated. Thus, the inner states of theprocessing vessels are prevented from being unstable and thereby beingnon-uniform during the time interval between the ending point of theconditioning and the starting point of the transfer of the wafers.Accordingly, in the semiconductor wafer process performed in eachprocessing vessel, e.g., the film formation process, uniformity of thefilms formed thereby (thickness and quality of the film) can beimproved.

Furthermore, the delay times D of the processing vessels A to D arecalculated such that the conditioning of each processing vessel iscompleted right before transferring the wafer thereto (step ST18). Basedon the calculated delay times, the start times of the conditionings areadjusted. By doing so, the amount of waiting time after completing theconditionings in the processing vessels can be considerably reduced (orcompletely removed theoretically).

Referring to FIGS. 4 and 8, the exemplary process in accordance with thepresent invention will be compared with a conventional process. As canbe seen in FIG. 8 showing the conventional process, there exist thewaiting time W_(A), W_(B), W_(C) and W_(D) different from each other,after the completion of the conditionings of the processing vessels A toD. In contrast, it can be seen in FIG. 4 that no waiting time W occursowing to controlling of the delay times D.

In the present invention, a processing vessel to be first conditioned ischosen from the processing vessels A to D through the steps (steps ST2to ST16 shown in FIG. 3) on the basis of the result of comparing theconditioning time S of a designated processing vessel with total time T(of the wafer transferring times C and the wafer processing times P ofone or more preceding processing vessels where processes are to beperformed prior to the process of the designated processing vessel andthe conditioning time of a processing vessel where a process is firstperformed among one or more processing vessels). For example, whenconditioning time (S2 as depicted in FIG. 4) of any processing vessel isgreater than the sum (S1+C1+P1 as depicted in FIG. 4) of all thesemiconductor wafer transferring times and all the processing times ofthe preceding processing vessels (depicted as processing vessel A in theexample shown in FIG. 4) and conditioning time of a processing vesselfirst processed, the conditioning of the processing vessel (depicted asprocessing vessel B in the example shown in FIG. 4) is initiated aheadof time such that the processing of the preceding processing vessel A isconcluded by the completion of the conditioning of the processing vesselB.

By this, the processes can be performed in the plurality of processingvessels with high efficiency, thereby improving a throughput of thesequential processing.

Parallel Processing

Hereinafter, the parallel processing of wafers by using the processingdevice 1 configured to have the processing vessels A to D for performingtherein an identical process will be described. Under suchconfiguration, one or more wafers are sequentially transferred into therespective processing vessels and then the identical process areperformed on one or more wafers H in the respective processing vesselsunder the control of the controller. Further, in a similar manner as inexecuting the sequential processing, the conditioning such as cleaning,precoating and the like is performed in each of the processing vessels Ato D to control the temperature, pressure and other parameters thereinto be appropriate for performing desired processes, prior totransferring the wafers thereinto.

In particular, when the wafers are sequentially loaded into theprocessing vessels A to D by the single transfer arm 2, as shown in FIG.1, the following scheme can be conceived. If until the completion oftransferring of one or more wafers into a specific processing vessel, aconditioning of another processing vessel for performing therein aprocess subsequent to that of the specific processing vessel is set tobe finished, the time intervals between the completion times of theconditionings and the start times of the processes can be the same inall the processing vessels and the wafers can be transferredefficiently.

Based on the aforementioned conception, there will now be explained thestarting point of a conditioning performed prior to a processing of afirst wafer in each processing vessel in executing the parallelprocessing. Herein, it is assumed that the parallel processing isexecuted by using a processing device having three processing vessels X,Y and Z, unlike the processing device 1 shown in FIG. 1. In this case,there are shown in FIGS. 5 and 6 the controlling processes of thecontroller until the starting points of the conditionings of theprocessing vessels X, Y, Z. FIG. 7 shows an exemplary timing diagram ofthe parallel processing executed based on the above. Further, S11, S12and S13 shown in FIG. 7 denote the amount of time required in performingthe conditionings of the processing vessels X, Y and Z, respectively;P11, P12 and P13, the amount of time required in performing theprocesses in the processing vessels X, Y and Z, respectively; and C11,C12 and C13, the amount of time required in transferring the wafers tothe processing vessels X, Y and Z, respectively (time periods betweenthe ending points of the conditionings and the starting points of theprocesses).

The controller makes a comparison of the conditioning times S todetermine a processing vessel to be first conditioned, as shown in FIG.5. Specifically, the respective conditioning times S11, S12, S13 of theprocessing vessels X, Y, Z are calculated in the step ST21, in a similarfashion as in the step ST1 shown in FIG. 3. Subsequently, thecomparisons of S11, S12 and S13 are conducted in the step ST22 and theconditionings are initiated in the processing vessels with the shortestconditioning time S and sequentially in the other processing vessels inorder of short conditioning times S. At this time, the starting pointsof the conditionings are controlled, such that concurrently with thecompletion of the transfer of the wafers to a processing vessel, theconditioning of another processing vessel to which next wafers aretransferred (hereinafter, may be referred to as a subsequent processingvessel) is finished. To be concrete, the starting points of theconditionings are controlled in a manner that the delay time D of thesubsequent processing vessel to which the next wafers are transferred iscalculated and the conditioning of the subsequent processing vessel isstarted after waiting for the calculated delay time D.

Depending on the comparing results of the step ST22 shown in FIG. 5,processes for calculating the delay times differ. FIG. 6 shows a case ofS13<S12<S11. In this case, a conditioning is initiated in the processingvessel Z having the shortest conditioning time S13 in the step ST23.Subsequently, the sum of the conditioning time and the transferring time(S13+C13) of the processing vessel Z is compared with the conditioningtime S12 of the subsequent processing vessel Y in the step ST24.

If the sum of S13 and C13 is smaller than S12 (S13+C13<S12) in the stepST24, the conditioning is initiated in the processing vessel Y in thestep ST25. Next, the sum of the conditioning time period and thetransferring time (S12+C12) of the processing vessel Y is compared withthe conditioning time S11 of the subsequent processing vessel X in thestep ST26. If the sum of S12 and C12 is smaller than S11 (S12+C12<S11),the conditioning of the processing vessel X is started in the step 27.However, if the sum of S12 and C12 is greater than S11 (S12+C12>S11),the delay time D11 of the processing vessel X is obtained by an equationD11=S12+C12−S11 in the step ST28. In the step 29, the conditioning ofthe processing vessel X is started after waiting for the delay time D11.

Further, if the sum of S13 and C13 is greater than S12 (S13+C13>S12) inthe step 24, the delay time D12 of the processing vessel Y is obtainedby calculating an equation D12=S13+C13−S12 in the step ST30. In the step31, the conditioning of the processing vessel Y is started after thedelay time D12 has elapsed.

Thereafter, the sum of the delay time, the conditioning time and thetransferring time (D12+S12+C12) of the processing vessel Y is comparedwith the conditioning time S11 of the subsequent processing vessel X inthe step ST32. If the sum of D12, S12 and C12 is smaller than S11(D12+S12+C12<S11) in the step ST32, the conditioning of the processingvessel X is started in the step ST33. However, if the sum of D12, S12and C12 is greater than S11 (D12+S12+C12>S11) in the step ST32, acalculation using an equation D11=D12+S12+C12−S11 is conducted to obtainthe delay time D11 of the processing vessel X in step ST34 and, in thestep ST35, the conditioning of the processing vessel X is started afterwaiting for the delay time D1.

As described above, a processing vessel to be initially conditioned isdetermined based on the conditioning times S of the processing vessels(steps ST21 and ST22) and, at the same time, the delay times D of theremaining processing vessels are calculated (steps ST28, ST30, ST34). Byusing the calculated delay times, the starting points of theconditionings of the processing vessels are controlled so that thetransferring of the wafers to a specific processing vessel and theconditioning of a processing vessel subsequent thereto are finished atthe same time (steps ST23, ST25, ST27, ST29, ST31, ST33, ST35). By doingso, the variation in intervals between the ending point of theconditioning and the starting point of the process in each processingvessel can be corrected. Therefore, the inner states of the processingvessels are prevented from being in a non-uniform state caused by theunstable processing parameters therein during the time intervals. As aresult, the uniformity of the semiconductor wafer process performed ineach of the processing vessels, e.g., uniformity of a film formation(thickness and quality of the film), can be improved.

Furthermore, the start times of the conditionings are controlled bycalculating the delay times D (step ST28, ST30, ST34) so that theconditionings are ended right before transferring the wafers into theprocessing vessels X, Y, Z. Such a control of the start times of theconditionings enables considerable reduction in the waiting timesoccurring after the completion of the conditionings in the processingvessels and efficient operation of the single transfer arm used incommon for the processing vessels. Accordingly, a processing efficiencyof the parallel processing by using the single transfer arm can beenhanced.

Described below are results of the exemplary parallel processing shownin FIG. 7 in accordance with the present invention in comparison withthat of the prior art shown in FIG. 9. In the prior art shown in FIG. 9,there are different waiting times (W_(X)=0), W_(Y), W_(Z) in theprocessing vessels X, Y, Z, respectively, after the completion of theconditionings. In contrast, there exists no waiting time W in FIG. 7 byusing the delay time D.

Furthermore, in the present invention, the conditioning is initiated ina processing vessel with the shortest conditioning time S andsequentially in the other processing vessels in order of shortconditioning times S. As a result, the processing efficiency in theplurality of processing vessels X, Y, Z is enhanced, which results inthe improvement of a throughput of the parallel processing.

Additional Embodiment

Though the above embodiment has been described with respect to theconditioning for processing the first wafer in each processing vessel,it can be applied to the processes of successive wafers subsequentthereto. For instance, exemplified in FIG. 7A there is a flow chart of aprocess for controlling the start of a conditioning performed prior to asecond process of the successive wafers (e.g., αth one) in theprocessing vessel C, in case of the sequential processing as shown inFIG. 4.

In FIG. 7A, at the moment of completing a process of an (α−1)th wafer inthe processing vessel C (step ST40), the amount of time left to performa process of an αth wafer in the processing vessel B is calculated (stepST41) Then the comparison of the amount of the calculated time left ofthe process in the processing vessel B with the amount of theconditioning time of the processing vessel C is carried out (step ST42).As the result of the comparison, if the amount of the time left isgreater (step ST43), the start time of the conditioning of theprocessing vessel C to be performed prior to the process of the αthwafer therein is set by using the aforementioned delay time (step ST44).On the other hand, if the remaining time is shorter (step ST43), thesame conditioning of the processing vessel C is started promptly (stepST45).

In addition, after the second wafer, the conditioning times may varywhen processing wafers, however, it is possible to predict the timerequired for a following conditioning by detecting the state of theprocessing vessel.

MODIFIED EXAMPLE

In the above preferred embodiments, both of the parallel processing andthe sequential processing are performed on the premises that thetransfer arm 2 is located at the center of the vacuum transfer vessel 4and, further, the distances between the transfer arm 2 and each of theprocessing vessels A to D (or X, Y, Z), the load lock chambers 6, 8 aresubstantially the same. Thus, the transferring times C1 to C4 (or C11 toC13) of the wafer are considered to be almost the same. However, if thetransferring time periods are quite different from each other, or if thetime intervals between the completion times of the conditionings and thestart times of the processes need to be identical to each other, thefollowing method may be used.

For instance, referring to FIGS. 3 and 4 illustrating the sequentialprocessing, if a maximum value of the different transferring times C1 toC4 is represented by C_(max), C1 to C4 are adjusted such thatC1=C2=C3=C4=C_(max). By doing so, the time intervals between thecompletion times of the conditionings and the start times of theprocesses can be made to be precisely identical to each other, though atime interval may be extended in some processing vessels. Further, bysetting C1 to C4 as C1=C2=C3=C4=Cmax+ΔC, C1 to C4 can be controlledarbitrarily by varying ΔC. Furthermore, in executing the parallelprocessing shown in FIGS. 6 and 7, if a maximum value of C11 to C13 isC_(max), the transferring time periods may be adjusted such thatC11=C12=C13=C_(max). By such adjustment, the time intervals of theprocessing vessels between the completion times of the conditionings andthe start times of the processes can be precisely identical with eachother, in executing the parallel processing.

In the above-described preferred embodiments of the present invention,the conditioning such as cleaning and precoating is performed toregulate the temperature, pressure, other parameters in each of theprocessing vessels to be suitable for performing a process, but theconditioning is not limited thereto. The conditioning may include otherprocesses which make the state in each processing vessel suitable forperforming therein the process. Further, the processing method of thepresent invention is applicable to a case of using the processing deviceincluding processing vessels for use in performing different processingsand processing vessels for use in performing an identical processingtogether.

Furthermore, there has been described in the preferred embodiments(excluding the additional embodiment) the start timings of theconditionings of the processing vessels controlled prior to transferringthe first wafer thereinto when processing the plurality of wafers but itis not limited thereto. In other words, the embodiment may be applied toa case of processing the subsequent wafers (or a case of resuming theprocess suspended due to a stopping of the device) or, to a case ofintermittently processing a plurality of wafers if the conditioning ofthe processing vessel is required to be performed prior to transferringthe wafer to be processed. The present invention is particularlyeffective when applied to a method for processing a plurality of wafers,where the conditioning is performed prior to the transfer of a firstwafer into processing vessels.

Though the above embodiments were applied to a situation where theplurality of processing vessels are employed, the embodiments may beapplied to a case in which a single processing vessel is employed.Specifically, by controlling a start time of a conditioning of thesingle processing vessel, a time interval between a completion time ofthe conditioning and a start time of a process can be reduced to theutmost and, therefore, the time interval effect is minimized. In thiscase, it is also effective to apply the present invention in which aconditioning of the processing vessel is performed prior to atransferring of a first wafer thereinto, when a plurality of wafers areprocessed.

Furthermore, though the single transfer arm is used in the presentembodiments, the present invention can be applied to a case of using aplurality of transfer mechanisms such as the transfer arm.

In accordance with the present invention, the promoted processingefficiency enables reduction of consumption of a processing gas orenergy such as a power.

While the invention has been shown and described with respect to thepreferred embodiments with reference to the accompanying drawings, thepresent invention is not limited thereto. The present invention will beunderstood by those skilled in the art that various changes andmodifications may be made without departing from the spirit and scope ofthe invention as defined in the following claims.

1. A semiconductor wafer processing method for performing a sequentialprocessing by using a plurality of processing vessels performingprocesses different from each other, the sequential processing beingcarried out by sequentially transferring a semiconductor wafer throughthe processing vessels, wherein a wafer processing in each processingvessel is performed after completing a conditioning of said eachprocessing vessel; and wherein a start time of a conditioning of a nextprocessing vessel is calculated to achieve a completed conditioningthereof such that a processing of a preceding processing vessel iscompleted synchronously therewith.
 2. A semiconductor wafer processingmethod for performing a sequential processing by using a plurality ofprocessing vessels performing processes different from each other, thesequential processing being carried out by sequentially transferring asemiconductor wafer through the processing vessels, wherein a waferprocessing in each processing vessel is performed after completing aconditioning of said each processing vessel; and wherein a start time ofa conditioning of a next processing vessel is controlled such that theconditioning of the next processing vessel is completed in harmony witha completion of a processing of a preceding processing vessel, wherein aprocessing vessel to be conditioned first among the processing vesselsis determined stepwise by comparing a conditioning time S of a specificprocessing vessel with a summation time T to determine a bigger oneamong the times S and T, the summation time T being a sum of atransferring time and a processing time of the wafer for each of one ormore preceding processing vessels in which a processing is carried outprior to the specific processing vessel and a conditioning time of aprocessing vessel for performing a processing first among the precedingprocessing vessels.
 3. A semiconductor wafer processing method forperforming a parallel processing by employing a plurality of processingvessels performing an identical processing and a transfer mechanismcommonly used for the processing vessels, the parallel processing beingcarried out by sequentially transferring semiconductor wafers to therespective processing vessels by the transfer mechanism and performingthe identical processing on a semiconductor wafer in each of theprocessing vessels, wherein a wafer processing in each processing vesselis performed after completing a conditioning of said each processingvessel; and wherein a start time of a conditioning of a processingvessel is calculated to achieve a completed conditioning thereof suchthat a transferring of a wafer to a preceding processing vessel to whicha wafer transferring is carried out prior to the processing vessel iscompleted synchronously therewith.
 4. A semiconductor wafer processingmethod for performing a parallel processing by employing a plurality ofprocessing vessels performing an identical processing and a transfermechanism commonly used for the processing vessels, the parallelprocessing being carried out by sequentially transferring semiconductorwafers to the respective processing vessels by the transfer mechanismand performing the identical processing on a semiconductor wafer in eachof the processing vessels, wherein a wafer processing in each processingvessel is performed after completing a conditioning of said eachprocessing vessel; and wherein a start time of a conditioning of aprocessing vessel is controlled such that the conditioning of theprocessing vessel is completed in harmony with a completion of atransferring of a wafer to a preceding processing vessel to which awafer transferring is carried out prior to the former processing vessel,wherein conditionings are sequentially initiated in the processingvessels in an ascending order of conditioning times.
 5. A semiconductorwafer processing method by using a plurality of processing vessels,wherein a wafer is transferred into each processing vessel and processedtherein after completing a conditioning of said each processing vessel;and wherein start times of conditionings of the processing vessels arecalculated to achieve completed conditionings such that time intervalsbetween completion times of the conditionings and processing start timesin the respective processing vessel are identical to each other.
 6. Themethod of claim 5, wherein, if transferring times to the respectiveprocessing vessels differ from each other, the time intervals betweencompletion times of the conditionings and processing start times in therespective processing vessel are set to be identical to a maximum valueof the transferring times.
 7. The method of claim 5, wherein, iftransferring times to the respective processing vessels differ from eachother, the time intervals between completion times of the conditioningsand processing start times in the respective processing vessel are setto be greater than a maximum value of the transferring times.
 8. Asemiconductor wafer processing device, comprising: a plurality ofprocessing vessels configured for performing processings different fromeach other on a semiconductor wafer, a conditioning of each processingvessel being performed before starting a processing thereof; and atransfer mechanism for transferring the wafer through the processingvessels, wherein a sequential processing is performed while sequentiallytransferring the wafer through the processing vessels by using thetransfer mechanism, a calculating unit for calculating, for eachprocessing vessel, a start time of a conditioning of a next processingvessel such that the conditioning of the next processing vessel iscompleted in harmony with a completion of a processing of a precedingprocessing vessel; and a conditioning control unit for startingconditionings of the respective processing vessels according to starttimes calculated by the calculating unit.
 9. A semiconductor waferprocessing device, comprising: a plurality of processing vesselsconfigured for performing an identical processing on a semiconductorwafer, a conditioning of each processing vessel being performed beforestarting a processing thereof; a transfer mechanism for transferring thewafer through the processing vessels, wherein a parallel processing isperformed while sequentially transferring the wafer through theprocessing vessels by using the transfer mechanism; a calculating unitfor calculating, for each processing vessel, a start time of aconditioning of a next processing vessel to achieve a completedconditioning thereof such that a transferring of a wafer to a precedingprocessing vessel is completed synchronously therewith; and aconditioning control unit for starting conditionings of the respectiveprocessing vessels according to start times calculated by thecalculating unit.